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Job Information

Intel Senior 3D-IC STCO Design Technology Engineer in Santa Clara, California

Job Description

The Group:

Intel's Advanced Design (AD) team resides within the Design Enablement (DE) organization, which collaborates closely with our partners in process technology, IP, and products spanning client/server and networking products. The primary focus of AD is to guide process technology definition, and design prototypes in Intel's latest process technology, supporting Intel's internal and external design customers.

The future of Moore's Law: 3D-IC

https://www.intel.com/content/www/us/en/newsroom/opinion/moore-law-now-and-in-the-future.html

https://www.zdnet.com/paid-content/article/moores-law-under-the-microscope-intel-advances-transistor-technology/

https://www.tomshardware.com/news/intel-teases-falcon-shores-xpu

The Role:

The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of future technologies, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO (System Technology Co-Optimization). The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System

Your responsibilities may include, but not be limited to:

  • Innovate on 3D-IC Heterogenous integration as a holistic co-optimization from System to Silicon in partnership with domain experts, extending DTCO to STCO (System Technology Co-Optimization).

  • Design analysis and optimization for 3D-IC Advanced Silicon and Packaging technology definition and certification.

  • Establish 3D-IC prototypes across market segments. Collaboration with Product teams to identify critical product characteristics and target setting requirements.

  • Engage with EDA providers on pathfinding of 3D-IC EDA feature requirements and 3D-IC design methodology.

  • Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable strong product differentiation

  • 3D-IC Test Chips validation of 3D-IC technology platforms and design methodology

#DesignEnablement

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a MS degree with 10+ years of experience or PhD degree with 8+ years of experience in Electrical Engineering or Computer Engineering and or related field.

Direct experience in the following areas:

  • Experience with design co-optimization and definition of Design Methodologies and for optimal Performance, Power, Area and Cost (PPAC) in advanced technologies.

  • Experience developing physical reference design flows and EDA vendor engagement.

  • Experience with prototypes, Testchip designs and/or Product designs.

  • Multiple clock domain and Low Power Design.

  • Scripting skills using a programming language such as Python, TCL, etc.

Preferred Qualifications:

Experience in the following:

  • External Foundry Experience.

  • Knowledge of semiconductor device physics.

  • Reference designs and TFM for STCO/3D-IC

Thermal Design Methodology and Power Distribution Network .

  • 3D Silicon and 3D Packaging technologies.

  • Experience with ARM-based system PPA optimization

Thermal Design Methodology and Power Distribution Network .

  • Circuit design, Standard Cell Library and Memory Architectures.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, OR, Hillsboro; US, TX, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $162,041.00-$259,425.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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