Job Information
Microsoft Corporation Senior Analog Computer Aided Design (CAD) Engineer in Redmond, Washington
The Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering organisation is seeking an engineer to join our Central Analog Computer-Aided Desing (CAD) Tools, Flows and Methodology (TFM) group leading physical verification across a multitude of technology nodes. This team drives state-of-the-art converged solutions, automation, and quality assurance checks across the analog and custom digital design domain from schematic entry through tape-out. This team supports numerous simultaneous projects within Microsoft by developing workflows for our design engineers so that they can deliver cutting-edge silicon solutions for Microsoft.
We are seeking a Senior Analog Computer-Aided Design Engineer to join our team!
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
Collaborate with the central CAD organization as well as across design teams to align roadmap for physical verification needs for custom IP as developed for Microsoft Silicon projects.
Maintain internal tooling used by design teams to execute physical verification tasks including LVS, DRC, ERC, and PERC.
Provide guidance and expertise to design teams when assessing new rules or debugging errors.
Audit physical verification settings to ensure alignment with internal customers and foundry partners.
Proactively engage with Electronic Design Automation (EDA) vendors to optimize flows with the latest cutting-edge technology.
Develop and maintain regression and test cases to exercise updates to rule decks and tool versions.
Identify opportunities for custom rule decks that enhance physical verification beyond vendor-provided flows.
Embody our Culture (https://www.microsoft.com/en-us/about/corporate-values) and Values (https://careers.microsoft.com/us/en/culture)
Qualifications
Required Qualifications:
7+ years of related technical engineering experience
o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
3+ years of experience with physical verification tools such as Siemens Calibre, Cadence Pegasus/PVS, Synopsys ICV or similar.
3+ years of experience using Linux for day-to-day activities in a professional or personal capacity.
3+ years of experience collaborating with a broad group of engineers to solve challenging problems.
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
MS in Electrical Engineering, Computer Engineering, Computer Science or equivalent work experience
10+ years of relevant experience
7+ years of experience in analog/custom IP design and/or CAD tool development in the physical verification domain
Understanding of object-oriented programming in languages such as Python or Ruby
Experience with git and continuous integration systems
In-depth experience writing custom DRC and LVS decks
In-depth experience with PERC debug and analysis
Familiarity with SKILL programming language for use in Virtuoso
Familiarity with layout construction in Cadence Virtuoso and/or Synopsys Custom Compiler in Advanced Nodes
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay
Microsoft will accept applications for the role until Sept 22, 2024.
#azurehwjobs #SCHIE
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .