Job Information
Microsoft Corporation Senior Engineer Logic Design in Multiple Locations, India
Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.
We are looking for a Senior Logic Design Engineer to work on leading edge IP development as part of the SCIPS Semi-custom and Central IP Silicon team. The candidate should be a motivated self-starter who will thrive in this cutting-edge technical environment.
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
We’re committed to a diverse and inclusive workplace and strongly encourage applicants from all background and walks of life. Difference makes us better.
Responsibilities
You will be responsible for all facets of design from working with architecture team, implementing the microarchitecture of IP blocks, RTL design, synthesis, static timing analysis, and silicon validation. Throughout the program you will be interacting with architects for feature definition, various design teams for leverage and collaboration, and software teams. Experience working with highspeed microarchitectures design required.
Qualifications
Required
Bachelor of Science in Electrical or Computer Engineering
8+ years of experience in hardware design
2+ years of experience in Synthesis, Timing constraints, Power Performance Area (PPA) trade-offs
7+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure.
Worked with leading-edge technologies 5 nm or smaller.
Experience in developing high speed CMOS designs.
Proficient in System Verilog, C/C++, and scripting languages such as Python, Ruby or Perl
Preferred
Knowledge of the ARM architecture and experience with high-speed IO protocols such as PCI Express or USB
Strong design knowledge of the industry standard bus interfaces such as AMBA AXI protocol
Experienced in Basic floor planning, static timing analysis, closure and working with Physical design team.
Experience with chip design quality through design and checklist reviews.
Good communication and self-motivated that can collaborate with larger teams within Microsoft.
Occasional travel
#SCHIEINDIA
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .