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SpaceX Sr. ASIC Design Engineer, DDR IP (Silicon Engineering) in Irvine, California

Sr. ASIC Design Engineer, DDR IP (Silicon Engineering) at SpaceX

Irvine, CA

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. ASIC DESIGN ENGINEER, DDR IP (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation SOCs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

  • Own the high quality release of the Memory Controller IP for SpaceX SoC designs, including triaging release/integration issues into IP defects and addressing issues

  • Responsible for Memory Controller/PHY IP core development and integration

  • Responsible for RTL design, synthesis, timing constraints, power estimation, and timing analysis using industry-leading CAD tools in the latest generation process technologies

  • Collaborate with chip architects, software engineers, and other subsystem owners to develop high performance Memory controller/PHY solutions

  • Write detailed design specifications and test plans in close collaboration with architecture, package and verification engineers

  • Support silicon bring-up, performance, and power characterization for memory subsystems

  • Drive functional verification including test plan reviews, and functional and code coverage as well as timing closure for your designs

BASIC QUALIFICATIONS:

  • BS in Electrical Engineering, Computer Engineering, or Computer Science

  • 8+ years of experience working with ASICs and the VLSI design flow

  • Experience in RTL development and verification using Verilog and/or SystemVerilog

PREFERRED SKILLS AND EXPERIENCE:

  • MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science

  • Knowledge of DDR/LPDDR DRAM protocols and experience analyzing/debugging DDR interfaces and protocols

  • Experience in the development of Memory Controller and PHY IPs

  • Experience working with Memory IP, Error checking Code (ECC), and building scalable, efficient flows and processes

  • Experience with designing state machines, data paths, arbitration and clock domain crossing (CDC) logic

  • Exposure to Design For Test (DFT), understanding of scan and writing DFT friendly RTL

  • Experience developing or integrating IPs with AMBA AXI, ACE-Lite, and CHI interfaces

  • Familiarity with Unified Power Format (UPF) for simulation and synthesis

  • Programming skills in C, PERL/Python

  • An eye for detail and ability to work with multi-functional teams to identify challenges and requirements and translate those into IP development items

  • Great communication and interpersonal skills

ADDITIONAL REQUIREMENTS:

  • Ability to work long hours and weekends as necessary to support critical milestones 

COMPENSATION & BENEFITS:

Pay range:

ASIC/FPGA Design Engineer/Senior: $160,000.00 - $220,000.00/per year

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

ITAR REQUIREMENTS:

  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here (https://www.pmddtc.state.gov/?id=ddtc_kb_article_page&sys_id=24d528fddbfc930044f9ff621f961987) .

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.

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