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Job Information

Intel SoC Design Engineer - Graduate Intern in Columbia, South Carolina

Job Description

Join Intel's Networking Design Team creating SoC solutions with next generation technologies. As part of the Physical and Structured Design team you will work with an experienced team of engineers motivated to deliver innovative solutions to physical synthesis, floor planning, place and route, timing and power optimizations.

Networking Silicon Solutions team develops SoC designs to accelerate Networking applications and cloud computing. The team works with Register Transfer Level (RTL) designs to implement structural physical designs through synthesis, floor planning, power-grid, clock tree design, place and route, RC-extraction, timing budgeting and closure to achieve targeted Performance/Power/Area. As a member of the team, you will learn to help verify designs through comprehensive sign-off tools in functional equivalence (FEV), timing/performance (STA), noise, layout design rules (DRC), reliability (RV), and power.

Responsibilities include but may not be limited to:

  • Full-chip electrical verification

  • Post-layout

  • Converging timing

  • Running a number of tools flows required to deliver high quality designs

An ideal candidates will have strong problem solving skills, and be a quick learner.

Length of internship estimate is 3 months with a possibility to extend.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

Minimum Qualifications:

  • Candidate must be pursuing a Master's or Ph.D. degree in Electrical Engineering, Computer Engineering or related field

  • Experience with Synopsys or Cadence physical design and signoff tools

  • SoC Design experience

Preferred Qualifications:

  • Experience in ASIC physical design

  • Knowledge of UPFs and power domain analysis

  • Knowledge of Ethernet, ORAN, PCIe, JESD, and 5G are helpful

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Covid Statement

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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