Job Information
Intel Principal Engineer -Memory Technology/Design Lead in Charleston, West Virginia
Job Description
About the Technology Development Group:
Technology Development (TD) is the heart and soul of Moore’s Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. TD’s more than 13,000 employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona.
The Design Enablement (DE) team in TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO) and delivers the Process Design Kits (PDKs) and Foundation IP (FIP) that designers need to support their product design work and fully leverage the technology. The Advanced Design (AD) team is part of Intel's DE Organization, and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology.
At Intel, DE is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies
About the Role:
As the Memory Technology/Design Lead, you will partner with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel's advanced CMOS process technologies.
Responsibilities:
Memory pathfinding activities and power, performance, area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
Memory bit-cell and complex periphery IC layout and automation.
Memory array/IP design, memory circuit innovation, test-chip design.
Pre-Si verification, post-Si validation, and debugging to enable yield and parametric tracking/ramp.
Internal and external customer engagement to enable optimized usage of Intel memory technology
Required Experience/Knowledge:
Knowledge of the CMOS ASIC design flow.
Custom digital circuit design, simulation, layout design, and verification
Knowledge of EDA tools used for analog, digital and mixed-signal circuit design.
Post-Si validation experience
Preferred Experience/Knowledge:
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files, ROM, DRAM, MRAM, etc.
Design trade-offs between power, performance, and area (PPA)
Design technology co-optimization (DTCO)
Qualifications
Master's or PhD in Electrical Engineering, Computer Engineering, or a related discipline
10+ years of professional experience.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
Annual Salary Range for jobs which could be performed in US, Colorado, New York, Washington, California: $186,760.00-$299,166.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.